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19-2626; Rev 0; 10/02
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
General Description
The MAX4719 low-voltage, low on-resistance (RON), dual single-pole/double throw (SPDT) analog switch operates from a single +1.8V to +5.5V supply. The MAX4719 features 20 RON (max) with 1.2 flatness and 0.4 matching between channels. The switch offers break-before-make switching (1ns) with tON <80ns and tOFF <40ns at +2.7V. The digital logic inputs are +1.8V logic compatible with a +2.7V to +3.6V supply. The switch is packaged in a chip-scale package (UCSPTM), significantly reducing the required PC board area. The chip occupies only a 2.0mm 1.50mm area and has a 4 3 bump array with a bump pitch of 0.5mm. The MAX4719 is also available in a 10-pin MAX package. o -3dB Bandwidth: >300MHz o Low 15pF On-Channel Capacitance o Single-Supply Operation from +1.8V to +5.5V o 20 RON (max) Switch 0.4 (max) RON Match (+3.0V Supply) 1.2 (max) RON Flatness (+3.0V Supply) o Rail-to-Rail(R) Signal Handling o High Off-Isolation: -55dB (10MHz) o Low Crosstalk: -80dB (10MHz) o Low Distortion: 0.03% o +1.8V CMOS-Logic Compatible o <0.5nA Leakage Current at +25C
Features
MAX4719
Applications
Cell Phones Battery-Operated Equipment Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Sample-and-Hold Circuits PDAs
Ordering Information
PART MAX4719EUB MAX4719EBC-T* TEMP RANGE -40C to +85C -40C to +85C PIN/BUMPPACKAGE 10 MAX 12 UCSP-12 TOP MARK -- ABJ
Note: UCSP package requires special solder temperature profile described in the Absolute Maximum Ratings section. *UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and environment. See the UCSP reliability notice in the UCSP Reliability section of this data sheet for more information.
UCSP is a trademark of Maxim Integrated Products, Inc. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
(BUMP SIDE DOWN) NC1 IN1 COM1 NO1 C1 C2 C3
MAX4719
GND B1 A1 A2 A3 NC2 IN_ IN2 COM2 NO2 0 1 MAX4719 V+ 1 NO_ OFF ON NC_ ON OFF NO1 2 COM1 3 IN1 4 NC1 5
MAX4719
10 NO2 9 8 7 6 MAX COM2 IN2 NC2 GND
SWITCHES SHOWN FOR LOGIC "0" INPUT
C4
B4 V+ UCSP
A4
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP MAX4719
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND) V+, IN_...................................................................-0.3V to +6.0V COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V) Continuous Current COM_, NO_, NC_ ...........................100mA Peak Current COM_, NO_, NC_ (pulsed at 1ms, 10% duty cycle)................................200mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW 12-Bump UCSP (derate 11.4mW/C above +70C) ....909mW ESD Method 3015.7 ...............................................................2kV Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Bump Temperature (soldering) (Note 2) Infrared (15s) ...............................................................+220C Vapor Phase (60s) .......................................................+215C
Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +3V Supply
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Analog Signal Range ANALOG SWITCH +25C On-Resistance (Note 5) RON V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 1.5V, 2.0V V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 3.3V, 0.3V V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 0.3V, 3.3V, or floating TMIN to TMAX +25C On-Resistance Match Between Channels (Notes 5, 6) RON TMIN to TMAX +25C On-Resistance Flatness (Note 7) RFLAT(ON) TMIN to TMAX +25C NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) TMIN to TMAX +25C TMIN to TMAX +25C Turn-On Time tON VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 1 TMIN to TMAX -0.5 -1 -1 -2 0.01 0.01 0.6 0.15 14 20 25 0.4 0.5 1.2 1.5 +0.5 +1 +1 +2 nA nA SYMBOL VCOM_, VNO_, VNC_ CONDITIONS TA TMIN to TMAX MIN 0 TYP MAX V+ UNITS V
COM_ On-Leakage Current (Note 8) DYNAMIC CHARACTERISTICS
ICOM_(ON)
40
80 100 ns
2
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20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
ELECTRICAL CHARACTERISTICS--Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Turn-Off Time SYMBOL tOFF CONDITIONS VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 2 VGEN = 2V, RGEN = 0; CL = 1.0nF, Figure 3 f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 4 f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 4 f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 4 f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 4 Signal = 0dBm, RL = 50; CL = 5pF, Figure 4 VCOM = 2VP-P, RL = 600 +25C +25C +25C +25C TMIN to TMAX TMIN to TMAX V+ = +3.6V, VIN_ = 0V or 5.5V TMIN to TMAX TMIN to TMAX V+ = +5.5V, VIN_ = 0V or V+ TMIN to TMAX -100 TA +25C TMIN to TMAX +25C Break-Before-Make Time Delay (Note 8) Charge Injection tBBM TMIN to TMAX +25C 1 18 -55 +25C -80 -80 +25C -110 300 0.03 9 20 MHz % pF pF dB dB 8 ns MIN TYP 20 MAX 40 50 ns UNITS
MAX4719
Q
pC
Off-Isolation
VISO
Crosstalk (Note 9)
VCT
On-Channel -3dB Bandwidth Total Harmonic Distortion NO_, NC_ Off-Capacitance Switch On-Capacitance DIGITAL I/O Input Logic High Voltage Input Logic Low Voltage Input Leakage Current POWER SUPPLY Power-Supply Range Supply Current
BW THD
CNO_(OFF) f = 1MHz, Figure 5 CNC_(OFF) CON f = 1MHz, Figure 5
VIH VIL IIN
1.4 0.5 +100
V V nA
V+ I+
1.8
5.5 1
V A
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3
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP MAX4719
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Analog Signal Range ANALOG SWITCH +25C On-Resistance (Note 5) RON V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 2.0V, 4.5V V+ = 5.5V; VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 4.5V, 1.0V V+ = 5.5V, VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 1.0V, 4.5V, or floating TMIN to TMAX +25C On-Resistance Match Between Channels (Notes 5, 6) RON TMIN to TMAX +25C On-Resistance Flatness (Note 7) RFLAT(ON) TMIN to TMAX +25C NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) TMIN to TMAX +25C TMIN to TMAX +25C Turn-On Time tON VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 2 TMIN to TMAX +25C Turn-Off Time tOFF TMIN to TMAX +25C Break-Before-Make Time Delay (Note 8) DIGITAL I/O Input Logic High Voltage Input Logic Low Voltage Input Leakage Current VIH VIL IIN V+ = 5.5V, VIN_ = 0V or V+ TMIN to TMAX TMIN to TMAX TMIN to TMAX -0.1 2.0 0.8 +0.1 V V A tBBM TMIN to TMAX 1 8 ns 20 -0.5 -1 -1 -2 +0.01 +0.01 0.4 0.15 12 20 25 0.4 0.5 1 1.2 +0.5 +1 +1 +2 nA nA SYMBOL VCOM_, VNO_, VNC_ CONDITIONS TA TMIN to TMAX MIN 0 TYP MAX V+ UNITS V
COM_ On-Leakage Current (Note 8) DYNAMIC CHARACTERISTICS
ICOM_(ON)
30
80 100 40 50 ns ns
4
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20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER POWER SUPPLY Power-Supply Range Supply Current V+ I+ V+ = 5.5V, VIN_ = 0V or V+ TMIN to TMAX TMIN to TMAX 1.8 5.5 1 V A SYMBOL CONDITIONS TA MIN TYP MAX UNITS
MAX4719
Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
UCSP parts are 100% tested at +25C only, and guaranteed by design over the specified temperature range. MAX parts are 100% tested at TMAX and guaranteed by design over the specified temperature range. The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive value is a maximum. Guaranteed by design for UCSP parts. RON = RON(MAX) - RON(MIN). Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Guaranteed by design. Between any two switches.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM
MAX4719 toc01
ON-RESISTANCE vs. VCOM
MAX4719 toc02
ON-RESISTANCE vs. VCOM
V+ = 5V
MAX4719 toc03
20 V+ = 1.8V 18
15 V+ = 3V 14 TA = +85C
15
14 TA = +85C
RON ()
RON ()
V+ = 2.5V V+ = 4.2V
14
12 TA = -40C TA = +25C
RON ()
16
13
13
12
12 V+ = 5V 0 1 2 3 4 5
11
11 TA = -40C TA = +25C 3 4 5
10 VCOM (V)
10 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
10 0 1 2 VCOM (V)
_______________________________________________________________________________________
5
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP MAX4719
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
LEAKAGE CURRENT vs. TEMPERATURE
MAX4719 toc04
LEAKAGE CURRENT vs. TEMPERATURE
MAX4719 toc05
CHARGE INJECTION vs. VCOM
MAX4719 toc06
700 V+ = 3V
800 V+ = 5V 600 LEAKAGE CURRENT (pA) COM ON-LEAKAGE 400 COM OFF-LEAKAGE
50
CHARGE INJECTION (pC)
LEAKAGE CURRENT (pA)
500
COM ON-LEAKAGE
40 CL = 1nF V+ = 5V 30 CL = 1nF V+ = 3V
300
COM OFF-LEAKAGE
200
20
100
0
10
-100 -40 -15 10 35 60 85 TEMPERATURE (C)
-200 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 1 2 3 4 5 VCOM (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX4719 toc07
SUPPLY CURRENT vs. LOGIC LEVEL
MAX4719 toc08
6 5 SUPPLY CURRENT (nA) 4 V+ = 5V 3 2 1 0 -40 -15 10 35 60 V+ = 3V
100
80 SUPPLY CURRENT (A) V+ = 5V 60
40 V+ = 3V 20
0 85 0 1 2 3 4 5 TEMPERATURE (C) LOGIC LEVEL (V)
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
MAX4719 toc09
TURN-ON/OFF TIME vs. SUPPLY VOLTAGE
MAX4719 toc10
2.0
100
1.6 LOGIC THRESHOLD (V) VTH+
80 tON/tOFF (ns)
1.2 VTH0.8
60
40
tON
0.4
20 tOFF
0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
TURN-ON/OFF TIME vs. TEMPERATURE
MAX4719 toc11
MAX4719
FREQUENCY RESPONSE
MAX4719 toc12
TOTAL HARMONIC DISTORTION vs. FREQUENCY
V+ = 3V RL = 600
MAX4719 toc13
60 50 40 30 20 10 0 -40 -15 10 35 60 tON, V+ = 3.0V tON, V+ = 5.0V
20 0 -20 ON-LOSS (dB)
V+ = 3V/5V
1
ON-LOSS THD (%) CROSSTALK 0.01 0.01 1 100 10 100 1k FREQUENCY (Hz) 10k 100k FREQUENCY (MHz)
tON/tOFF (ns)
-40 -60 -80 -100 OFF-ISOLATION
0.1
tOFF, V+ = 3.0V
tOFF, V+ = 5.0V 85
-120 -140 0.0001
TEMPERATURE (C)
Pin Description
PIN UCSP A1 A2 A3 A4 B1 B4 C1 C2 C3 C4 MAX 7 8 9 10 6 1 5 4 3 2 NAME NC2 IN2 COM2 NO2 GND V+ NC1 IN1 COM1 NO1 FUNCTION Analog Switch 2--Normally Closed Terminal Digital Control Input for Analog Switch 2 Analog Switch 2--Common Terminal Analog Switch 2--Normally Open Terminal Ground Positive-Supply Voltage Input Analog Switch 1--Normally Closed Terminal Digital Control Input for Analog Switch 1 Analog Switch 1--Common Terminal Analog Switch 1--Normally Open Terminal
Detailed Description
The MAX4719 high-speed, low-voltage, 20 RON, dual SPDT analog switch operates from a single +1.8V to +5.5V supply. The switch features break-before-make switching operation and fast switching speeds (tON = 80ns (max), tOFF = 40ns (max)).
Applications Information
Digital Control Inputs
The MAX4719 logic inputs accept up to +5.5V regardless of supply voltage. For example, with a +3.3V supply, IN_ can be driven low to GND and high to +5.5V allowing for mixing of logic levels in a system. Driving the control logic inputs rail-to-rail minimizes power consumption. For a +3V supply voltage, the logic thresholds are 0.5V (low) and 1.4V (high); for a +5V supply voltage, the logic thresholds are 0.8V (low) and 2.0V (high).
Analog Signal Levels
The on-resistance of the MAX4719 changes very little for analog input signals across the entire supply voltage range (see the Typical Operating Characteristics). The switches are bidirectional, so the NO_, NC_, and COM_ pins can be either inputs or outputs.
_______________________________________________________________________________________
7
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP MAX4719
Power-Supply Sequencing and Overvoltage Protection
Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current-limited. usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user's PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Maxim's qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim's website at www.maxim-ic.com.
UCSP Package Considerations
For general UCSP package information and PC layout considerations, please refer to the Maxim Application Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and
Chip Information
TRANSISTOR COUNT: 235 PROCESS: BiCMOS
Test Circuits/Timing Diagrams
MAX4719
V+ V+ COM_ RL 300 IN_ LOGIC INPUT GND SWITCH OUTPUT 0V t ON LOGIC INPUT VOUT CL 35pF VOUT 0.9 x V0UT t OFF 0.9 x VOUT VIH 50% VIL t r < 5ns t f < 5ns
VN_
NO_ OR NC_
VOUT = VN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL RL + RON
(
)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 1. Switching Time
MAX4719
V+ V+ LOGIC INPUT COM_ RL 300 GND VOUT VOUT CL 35pF
VIH 50% VIL
VN_
NC_ NO_ IN_
LOGIC INPUT
0.9 x VOUT tBBM
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval 8 _______________________________________________________________________________________
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
Test Circuits/Timing Diagrams (continued)
V+
MAX4719
MAX4719
V+ RGEN NC_ OR NO_ GND IN_ OFF ON Q = (V OUT )(C L ) COM_ CL VOUT VOUT IN OFF ON
VOUT
OFF
V GEN
VIL TO VIH
IN
OFF
IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 3. Charge Injection
+5V 10nF NETWORK ANALYZER 0V OR V+ IN_ V+ COM1 VIN 50 50
V OFF-ISOLATION = 20log OUT VIN V ON-LOSS = 20log OUT VIN V CROSSTALK = 20log OUT VIN
NC1 50
MAX4719
NO1* GND VOUT MEAS REF
50
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
Figure 4. On-Loss, Off-Isolation, and Crosstalk
10nF
V+
V+ COM_
MAX4719
VIL OR VIH
IN CAPACITANCE METER f = 1MHz NC_ or NO_ GND
Figure 5. Channel Off/On-Capacitance _______________________________________________________________________________________ 9
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP MAX4719
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12L, UCSP 4x3.EPS
10
______________________________________________________________________________________
20, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
MAX4719
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b D1 A1
E2 c E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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